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CS 240: Operating Systems
14 Chunks Indexed
Slide 14 of 42: Two-Level Page TablesSource Document
Virtual Address Translation Hierarchy32-bit Architecture
Directory (10b)Root Index
Table (10b)PTE Index
Offset (12b)Page Byte

Key Principle Cited by AI:

“Unlike linear single-level page tables where entries must reside continuously in memory, a two-level table allocates secondary tables on demand. Unused address ranges require zero secondary page tables.”

Section: Memory Management
Grounded Course Tutor
Why do multi-level page tables save memory compared to single-level?

Because virtual memory is sparse! In a linear table, you must allocate entries for all 4GB of address space even if the program only uses 10MB.

With multi-level tables, intermediate page directories remain unallocated until that memory range is actually mapped.

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CS 240: Memory HierarchyVerified Grounding

Spatial Locality refers to accessing data elements that are physically stored near one another in memory.

[Lecture 6, Slide 12: Cache Lines][Handout 3, Page 4]
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Which page replacement policy minimizes theoretical misses?

Correct: OPT replaces the page that will not be used for the longest time in the future.

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CS 240

Operating Systems

14 documents

BIOL 110

Cellular Biology

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MATH 215

Multivariable Calc

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Grounded Course Tutor
CS 240 · Lec 08

How does a Translation Lookaside Buffer (TLB) prevent a memory penalty?

Read “Lec 08: Memory Hierarchy, Slide 18”

The TLB is an on-chip hardware cache of recent virtual-to-physical address translations. When a TLB hit occurs, translation finishes in <1 cycle—completely bypassing the multi-step page table walk in physical RAM.

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